In high resolution digital-to-analog converters (DACs), performance metrics such as linearity and noise are nominally determined by the matching of parameters derived from physical quantities in the construction of the DACs on an integrated circuit (IC), such as width, length, thickness, doping, etc. As a general rule, for each additional bit of performance in the DAC, parameter matching needs to be twice as tight. This translates to an increase by a factor of four in the IC area required by the DAC. When the DAC resolution is in the 16-bit range, it is no longer practical or economical to use size alone to achieve the required matching.
Over-sampled (delta-sigma or Δ-Σ) DACs alleviate the need for raw matching using single-bit conversion (so called 1-bit DACs in CD players). A single-bit DAC has only two points in a transfer function of the DAC, and thus is inherently linear. The function of a Δ-Σ modulator with a one-bit quantizer is to approximate a high-resolution, low-frequency signal with a high-frequency two-level signal. The drawback is that this produces large amounts of out-of-band, for example, high frequency, noise.
Multi-bit DACs have the advantage of significantly increasing the precision limit of the single-bit DAC. The major drawback of the multi-bit DAC is the non-linearity presented by the imperfect analog circuit mismatches. Specifically, the non-linearity stems from the mismatching between the unit DAC elements, and causes significant performance degradation. (For purposes of this application, the terms “DAC element” and “unit DAC element” may be used interchangeably.)
One method of reducing this non-linearity is dynamic element matching (DEM). DEM is a method of randomizing the use of the individual unit DAC elements so that each DAC element is used equally as often, and averaging the errors in each DAC element. Two common methods of DEM are tree-structured DEM and data weighted averaging (DWA) DEM. In tree-structured DEM, incoming code is shuffled before it enters the unit DAC elements. Tree-structured DEM is called such because the input code is split into two numbers, which are shuffled and then split into four numbers, which are shuffled, and so on.
In DWA DEM, a pointer keeps track of the number of DAC elements in use. For each unit DAC element used when a sample of thermometer code is input, the pointer moves to the next DAC element. If the next DAC element in line is unused, then the pointer does not move, but stays pointing at the unused DAC element. When the next sample of thermometer code is input, the first DAC element used is the one to which the pointer is pointing, and successive DAC elements are used in line order. In both the tree-structured method and the DWA method, each DAC element is used as often as every other DAC element, reducing any non-linearity.
However, for multi-bit Δ-Σ modulators, it has been found that using tree-structured and DWA algorithms causes in-band tones for a certain level of input signals. This effect can be tracked back to the cyclic nature of the selection of unit DAC elements when the input to the modulator is small. When the modulator's input magnitude is very small, the large portion of the DAC input codes are almost exclusively concentrated at the middle of the full scale of the modulator's internal DAC elements. For data with a sample rate of Fs, the consecutive occurrence of mid-code into the DAC results in the notable tones with frequencies around Fs/2 appearing in the modulator output spectrum.
Take an example of a nine-level DAC that uses eight unit DAC elements. The input digital code ranges from 0 to 8, with the mid-code of 4. Assume the errors for the unit DAC elements are ei, i=0, 1, . . . , 7. For the DWA with input DAC sequence codes 4, 4, 4, 4, . . . , the DAC output noise manifests as a Fs/2-periodic sequence, e0+e1+e2+e3, e4+e5+e6+e7, e0+e1+e2+e3, e4+e5+e6+e7, . . . , where Fs is the sampling frequency. For the tree-structured DEM, the same input codes produce the DAC output as another Fs/2-periodic sequence, e0+e2+e4+e6, e1+e3+e5+e7, e0+e2+e4+e6, e1+e3+e5+e7, . . . . The dither to the quantizer of the modulator does not help too much, as its effect is merely to amplitude-modulate the Fs/2 tone. For example, the codes 3, 5, 3, 5 for DWA produces the DAC output as an Fs/2-periodic sequence, e0+e1+e2, e3+e4+e5+e6+e7, e0+e1+e2, e3+e4+e5+e6+e7, . . . . The similar amplitude-modulated Fs/2 tones are generated for the tree-structure with the same input codes.
There have been several patents and other references addressing the tone problems and the techniques to remove it. See, e.g., I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters”, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, pp. 808–817, vol. 44, no. 10, October 1997; J. Grilo et al., “A 12-mW ADC Delta-Sigma Modulator with 80 dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiver”, IEEE Journal of Solid-State Circuits, pp. 271–278, vol. 37, March 2002; J. Welz et al., “Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters”, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, pp. 1014–1027, vol. 48, no. 11, November 2001; R. Adams et al., “A 113-db SNR Oversampling DAC with Segmented Noise-Shaped Scrambling”, IEEE Journal of Solid State Circuits, pp. 1871–1878, vol. 33, no. 12, December 1998; T. Kwan et al., “A Stereo Multibit ΣΔ DAC with Asynchronous Master-Clock Interface”, IEEE Journal of Solid-State Circuits, pp. 1881–1887, vol. 31, no. 12, December 1996; A. Yasuda et al., “A Third-Order ΣΔ Modulator Using Second-Order Noise-Shaping Dynamic Element Matching”, IEEE Journal of Solid-State Circuits, pp. 1879–1886, vol. 33, no. 12, December 1998; R. Radke et al., “A Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averaging”, IEEE Custom Integrated Circuits Conference, 1999, pp. 125–128; R. Baird and T. S. Fiez, “Improved ΔΣ DAC Linearity Using Data Weighted Averaging”, IEEE International Symposium, vol. 1, pp. 13–16, 1995; R. Radke et al., “A 14-bit Current-Mode ΣΔ DAC Based Upon Rotated Data Weighted Averaging”, IEEE Journal of Solid State Circuits, vol. 35, no. 8, August 2000; Kuan-Dar Chen and T. Kuo, “An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither”, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no. 1, January 1999; F. Chan and B. Leung, “Some Observations on Tone Behavior in Data Weighted Averaging”, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 500–503, 1998; M. Vadipour, “Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in ΣΔ Modulators”, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, no. 11, November 2000; G. Zelniker and F. Taylor, Advanced Digital Signal Processing: Theory and Applications, Marcel Dekker, Inc., New York, 1994, pp. 357–364; and S. R. Norsworthy et al., “Delta-Sigma Data Converters: Theory, Design, and Simulation”, pp. 185–186, IEEE Press, New York, 1997.
Dithering has been proposed for removal of these tones (see R. Radke, “Improved”, cited above), but the improvement in tonal performance is limited and results in signal-to-noise ratio (SNR) degradation. Another technique uses extra unit DAC elements to move the tones out of the baseband (see Kuan-Dar Chen, cited above). Rotational DWA switches randomly between different patterns for DAC selection (see R. Radke, “Spurious” and R. Radke, “14-bit”, cited above), but the ROM hardware that stores the transition states is not trivial. Another technique adds an offset to shift the tone out of the baseband (see M. Vadipour, cited above). In addition, randomized DWA is used to reduce the hardware complexity of the rotational DWA. This tends to sacrifice SNR performance. For the tree-structured DEM (see I. Galton, J. Grilo, and J. Welz, cited above), a dither at every other sample helps reduce the tone, but this too sacrifices SNR performance.